[Project funded bythe Department of Science and Technology, Government of India, under India-Australia Strategic Research Fund.]
(In collaboration with Professor Michelle Simmons, University of New South Wales, Sydney, Australia.)
Noise – the stochastic variation in the characteristics of electronic devices has a notorious reputation for degrading the performance and reliability of both digital and analog circuits. In fact, the International Technology Roadmap for Semiconductors (ITRS) has identified noise as one of the formidable challenges of miniaturizing silicon devices to nano-scale dimensions. Low frequency noise is expected to increase with down-scaling of metal oxide semiconductor (MOS) devices, both due to decrease in the gate area and uncertainty in the number and location of dopants. Electronic noise is therefore of serious concern for envisaged nanoscale and quantum electronic devices, such as sub 30nm metal-oxide semiconductor field effect transistors (MOSFETs) and silicon based solid state quantum computer proposals.
The intention of this project is to investigate the sources of noise, especially the low frequency Flicker noise, in highly confined, nanoscale silicon devices.
To date there have been very few studies where the local environment of the electrons is probed electronically, due to
However, by the recent success in combining two cutting edge technologies, i.e. molecular beam epitaxy (MBE) and scanning tunneling microscopy (STM), it is now possible to fabricate nanoscale transistors wherein, the density and the location of the dopants, and therefore the local environment of the charge carriers, can be precisely controlled.
This joint project will study conventional (time-averaged) and noise (time-dependent) transport in nanoscale transistors and thereby determine the impact of intrinsic fluctuations in the performance and reliability of sub 30nm MOSFETs and more exotic quantum devices such as a silicon based quantum computer.
Atomic scale transistor realized by incorporating phosphorus atoms in a layer within silicon matrix with STM lithography. These devices have been prepared in the research group of Professor Michelle Simmons at University of New South Wales.
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